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mt9v115: 1/13-inch vga soc digital image sensor features ? mt9v115 ds rev. e pub. 5/15 en 1 ?semiconductor components industries, llc 2015, 1/13-inch system-on-a-chip (soc) cmos digital image sensor mt9v115 datasheet, rev. e for the latest datasheet, please visit www.onsemi.com features ? superior low-light performance ? ultra-low-power ?vga video at 30fps ? internal master clock generated by on-chip phase locked loop (pll) oscillator ? electronic rolling shutter (ers), progressive scan ? integrated image flow processor (ifp) for single-die camera module ? one-time programmable memory (otpm) ? automatic image correction and enhancement, including four-channel lens shading correction ? arbitrary image scalin g with anti-aliasing ? supports itu.r.656 format (progressive scan version) ? two-wire serial interface providing access to registers and microcontroller memory ? selectable output data format: ycbcr, 565rgb, processed bayer, raw8- and raw8+2-bit, bt656* ? parallel data output ?programmable i/o slew rate ? mipi serial mode supporting 8-bit and 10-bit data streams ? independently configurable gamma correction ? direct xdma access (reducing serial commands) ? integrated hue rotation applications ? mobile phones ?pc and notebook cameras ? gaming systems general description on semiconductor's mt9v115 is a 1/13-inch cmos digital image sensor with an active-pixel array of 648h x 488v. it includes sophisticated camera functions such as auto exposure control, auto white balance, black level control, flicker detection and avoidance, and defect correction. it is designed for low light per- formance. it is programmable through a simple two- wire serial interface. the mt9v115 produces extraordi- narily clear, sharp digital pictures that make it the per- fect choice for a wide rang e of applications, including mobile phones, pc and notebook cameras, and gam- ing systems. * supports itu-r bt.656 format with odd timing code. bt656 is used on interlaced output but this is a progressive scan output table 1: key parameters parameter typical value optical format 1/13-inch active pixels 648 x 488= 0.3 mp (vga) pixel size 1.75 ? m color filter array rgb bayer shutter type electronic rolling shutter (ers) input clock range 4 C 44 mhz output clock maximum parallel 22 mhz mipi 176 mbps output parallel 8 bit mipi 8 bit, 10 bit frame rate, full resolution 30 fps responsivity 1.88 v/lux*sec snr max (temporal) 34.1 db dynamic range 64 db supply voltage digital 1.8 v analog 2.8 v mipi 2.8 v power consumption 55 mw(est.) operating temperature (ambient) -t a C30 c to +70 c chief ray angle 24 package options wafer, csp
mt9v115 ds rev. e pub. 5/15 en 2 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor ordering information ordering information table 2: available part numbers part number product description orderable product attribute description mt9v115d00stck22ec1-200 vga 1/13"soc die sales, 200 ? m thickness MT9V115EBKSTC-CR vga 1/13"cis soc chip tray without protective film mt9v115w00stck22ec1-750 vga 1/4" soc wafer sales, 750 ? m thickness
mt9v115 ds rev. e pub. 5/15 en 3 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 register and variable descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 slave address selection in dual camera application (only for pa rallel not supported in serial) . . . . . . . . . . . . . .37 one-time programming memory (otpm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 spectral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 power sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
mt9v115 ds rev. e pub. 5/15 en 4 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor list of figures list of figures figure 1: mt9v115 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: typical configuration (connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 3: hard standby mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 4: soft standby mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 5: pixel data timing example: 8+2 bayer format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 6: frame timing, fv, and lv structur e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 7: sensor core block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 8: pixel color pattern detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 10: six pixels in normal and column mirror readout mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 11: eight pixels in normal and column skip 2x readout mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 12: pixel readout (no skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 13: pixel readout (x_odd_inc = 3, y_odd_inc = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 14: image flow processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 16: gamma correction curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 17: 0 hue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 18: ?22 hue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 19: +22 hue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 20: bt656 image data with odd sav/eav codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 21: single read from random locati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 22: single read from current location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 23: sequential read, start from rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 24: sequential read, start from curre nt location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 25: single write to random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 26: sequential write, start at rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 27: dual camera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 28: chief ray angle (cra) vs. image height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 29: quantum efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 31: mipi clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 32: mipi data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 33: two-wire serial bus timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 34: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 35: power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
mt9v115 ds rev. e pub. 5/15 en 5 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor list of tables list of tables table 1: key parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2: available part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 3: signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4: pad functionality based on output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5: status of output signals during reset and standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6: hard standby signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7: soft standby signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8: ycbcr output data ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9: rgb ordering in default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 10: 2-byte bayer format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 11: data formats supported by mipi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 12: summary of mt9v115 variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 13: absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 14: operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 15: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 16: operating/standby current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 17: ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 18: mipi timing measurements : clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 19: mipi timing measurements: data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 20: mipi high speed (hs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 21: mipi low power (lp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 22: two-wire serial interfac e timing data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 23: power- up signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 24: power-down supply rail timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
mt9v115 ds rev. e pub. 5/15 en 6 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description functional description on semiconductor?s mt9v115 is a 1/13-inch vga cmos digital image sensor with an integrated advanced camera system. this camera system features a microcontroller (mcu), a sophisticated image fl ow processor (ifp), a serial port, and a parallel port. the microcontroller manage s all functions of the camera system and sets key operating parameters for the sensor core to optimize the quality of raw image data entering the ifp. the sensor core consists of an active pixe l array of 648 x 488 pixels with programmable timing and control circuitry. it also includes an analog signal chain with automatic offset correction, programmable gain, and a 10- bit analog-to-digital converter (adc). the entire system-on-a-chip (soc) has an ultra-low power operational mode and a superior low-light performance that is particularly suitable for mobile applications. the mt9v115 features on semiconductor?s brea kthrough low-noise cmos imaging tech- nology that achieves near-ccd image qualit y (based on signal-t o-noise ratio and low- light sensitivity) while maintaining the inherent size, cost, and integration advantages of cmos. architecture overview the mt9v115 combines a vga sensor core with an ifp to form a stand-alone solution for both image acquisition and processing. both the sensor core and the ifp have internal registers that can be controlled by the user. in normal operation, an integrated microcontroller autonomo usly controls most aspects of operation. the processed image data is transmitted to the host system throug h the serial or parallel bus. figure 1 shows the major functional blocks of the mt9v115. figure 1: mt9v115 block diagram pixel array (648 x 488) column control row control pll ram rom uc ontroller analog processing adc digital image processing (soc) fifo cci serial interface s data sclock fv , lv,pixclk, d out [7:0] standby extclk v d d p l l v d d_phy v aa v dd v ddio v pp a gnd d gnd image data bus register bus serial parallel pixclk dout[5:0] fv, lv d out [7:6] data_p, data_n clk_p, clk_n data_p/d out [7] data_n/d out [6] clk_p/fv clk_n/lv 4 4 4 11 7
mt9v115 ds rev. e pub. 5/15 en 7 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description sensor core the mt9v115 has a color image sensor with a bayer color filter arrangement and a vga active-pixel array with electronic rolling shu tter (ers). the sensor core readout is 10 bits. the sensor core also supports separate analog and digital gain for all four color channels (r, gr, gb, b). image flow processor (ifp) the advanced ifp features and flexible pr ogrammability of the mt9v115 can enhance and optimize the image sensor performance. built-in optimization algorithms enable the mt9v115 to operate with factory settings as a fully automatic and highly adaptable system-on-a-chip (soc) for most camera systems. these algorithms include shading correction, defect correction, color interpolation, edge detection, color correction, aperture correction, and image formatting with crop- ping and scaling. microcontroller unit (mcu) the mcu communicates with all functional blocks by way of an internal on semicon- ductor proprietary bus interface. the mcu firmware executes the automatic control algorithms for exposure and white balance. system control the mt9v115 has a phase-locked loop (pll) os cillator that can generate the internal sensor clock from the common system clock. the pll adjusts the incoming clock frequency up, allowing the mt9v115 to run at almost any desired resolution and frame rate within the sens or?s capabilities. low-power consumption is a very important requirement for all components of wireless devices. the mt9v115 provides power-conservi ng features, including an internal soft standby mode and a hard standby mode. a two-wire serial interface bus enables read and write access to the mt9v115?s internal registers and variables. the internal registers control the sensor core, the color pipeline flow, the output interface, auto white balance (awb) and auto exposure (ae). output interface the output interface block can select either raw data or processed data. image data is provided to the host system by an 8-bit parall el port (up to 22mb/sec) or by a serial mipi port (up tp 176mbps with 8-bit and 10-bit support). the parallel output port provides 8- bit ycbcr, yuv, 565 rgb, bt656, processed bayer data or extended 10-bit bayer data achieved using 8+2 format. system interfaces figure 2 on page 8 shows typical mt9v115 devi ce connections. for low-noise operation, the mt9v115 requires separate power supplies for analog and digital sections of the die. both power supply rails should be decoupled from ground using capacitors as close as possible to the die. the use of inductance filters is not recommended on the power supplies or output signals.
mt9v115 ds rev. e pub. 5/15 en 8 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description the mt9v115 provides dedicated signals for digital core and i/o power domains that can be at different voltages. the pll and analog circuitry require clean power sources. table 3, ?signal descriptions,? on page 10 pr ovides the signal descriptions for the mt9v115. figure 2: typical configuration (connection) notes: 1. this typical configuration shows only one scenar io out of multiple possibl e variations for this sen- sor. 2. on semiconductor recommends a minimum 1.5k ?? resistor value for the two-wire serial interface r pull - up ; however, greater values may be used for slower transmission speed. 3. only one mode, mipi or parallel can be used at one time 4. v dd _phy requires 2.8v nominal in mipi mode, but can take v dd _io setting in parallel mode. 5. as a minimum, on semiconductor recommends that a 0.1 ? f decoupling capacitor for each power supply is mounted as close as possible to the pa d inside the module. actual values and numbers may vary depending on layout and design considerations. analog power s data s clk pixclk standby a gnd i/o power v aa two-wire serial interface parallel port r pull-up 2 standby mode extclk external clock in (4C44 mhz) d out [5:0] v dd _io digital core power v dd v pp gnd, gnd_pll pll power v dd _pll otpm power (optional) data_p/d out [7] data_n/d out [6] clk_p/fv clk_n/lv mipi/parallel port phy power 4 v dd _phy 0.1f v dd _io 5 v dd _pll 5 v dd 5 v aa ,v dd _phy 5 or/and 3
mt9v115 ds rev. e pub. 5/15 en 9 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description decoupling capacitor recommendations the minimum recommended decoupling capacitor recommendation is 0.1f per supply in the module. it is important to provide clean, well re gulated power to each power supply. the on semiconductor recommendation for capacitor placement and values are based on our internal demo camera design and verified in hardware. note: since hardware design is influenced by many factors, such as layout, operating condi- tions, and component selection, the customer is ultimately responsible to ensure that clean power is provided for their own designs. in order of preference, on semiconductor recommends: 1. mount 0.1f and 1f decoupling capacitors for each power supply as close as possi- ble to the pad and place a 10 f capacitor nearby off-module. 2. if module limitations allow for only six decoupling capacitors for a three-regulator design (v dd _pll tied to v aa ), use a 0.1f and 1f capacitor for each of the three reg- ulated supplies. on semiconductor also recommends placing a 10f capacitor for each supply off-module, but close to each supply. 3. if module limitations allow for only three decoupling capacitors, a 1f capacitor for each of the three regulated supplies is preferred. on semiconductor recommends placing a 10f capacitor for each supply off-module but closed to each supply. 4. if module limitations allow for only three decoupling capacitors, a 0.1f capacitor for each of the three regulated supplies is preferred. on semiconductor recommends placing a 10f capacitor for each supply off-module but close to each supply. 5. priority should be given to the v aa supply for additional decoupling capacitors. 6. inductive filtering components are not recommended. 7. follow best practices when performing physical layout. refer to technical notes tn-09-131 and tn-09-214.
mt9v115 ds rev. e pub. 5/15 en 10 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description signal descriptions table 3: signal descriptions name type description extclk input input clock signal standby input controls sensor's standby mode, active high s clk input two-wire serial interface clock s data i/o two-wire serial interface data frame_valid (fv) output identifies rows in the active image line_valid (lv) output identifies pixels in the active line pixclk output pixel clock d out [7:0] output d out [7:0] for 8-bit image data output clk_n output differential mipi clock clk_p output differential mipi clock data_n output data_n output differential mipi data data_p output data_p output differential mipi data v dd supply digital power d gnd supply digital ground v dd _io supply i/o power supply v pp supply otpm power supply v dd _pll supply pll power v dd _phy supply mipi power supply gnd_pll supply pll ground v aa supply analog power a gnd supply analog ground table 4: pad functionality based on output modes parallel output mipi output d out [6] data_n d out [7] data_p frame_valid clk_p line_valid clk_n
mt9v115 ds rev. e pub. 5/15 en 11 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description power-on reset the mt9v115 includes a power-on reset featur e that initiates a reset upon power-up. a soft reset is issued by writing command s through the two-wire serial interface. two types of reset are available: ? a soft reset is issued by writing comma nds (sysctl r0x001a[0] = 1)through the two- wire serial interface register 0x1a bit[4:6] during normal operation. ?an internal power-on reset the output states after hard rese t are shown in table 5 on page 11. a soft reset sequence to the sensor has the same effect as the hard reset and can be acti- vated by writing to a register through the two-wire serial interface. on-chip power- onreset circuitry can generate an internal rese t signal in case an external reset is not provided. the reset_bar signal has an internal pull-up resistor and can be left floating. standby the mt9v115 supports two different standby modes: 1. hard standby mode 2. soft standby mode the hard standby mode is invoked by asserting the standby pin. it then disables all of the digital logic within the image sensor, and only supports being awoken by de- asserting the standby pin. the soft standby mo de is enabled by a single register access, which then disables the sensor core and most of the digital logic. however, the serial interface is kept alive, which allows the imag e sensor to be awoken via a serial register access. all output signal status during standby are shown in table 5. hard standby mode the mt9v115 can enter hard standby mode by using external standby signal, as shown in figure 3. the two-wire serial interface and ifp block shut down even when extclk is running during hard standby mode. table 5: status of output si gnals during reset and standby signal reset post-reset standby d out [7:0] high-z high-z high-z pixclk high-z high-z high-z lv high-z high-z high-z fv high-z high-z high-z clk_n high-z 0 0 clk_p high-z 0 0 data_n high-z 0 0 data_p high-z 0 0
mt9v115 ds rev. e pub. 5/15 en 12 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description entering standby mode 1. assert standby signal (high). exiting standby mode 1. de-assert standby signal (low). 2. part is now ready for streaming. figure 3: hard standby mode operation note: in hard standby mode, extclk is automatically gated off, and the two-wire serial interface is not active. soft standby mode the mt9v115 can enter soft standby mode by writing to a sysctl register through the two-wire serial interface, as shown in figu re 4. extclk can be stopped to reduce the power consumption during soft standby mode. however, since two-wire serial interface requires extclk to operate, on semiconductor recommends that extclk run contin- uously. table 6: hard standby signal timing symbol parameter min typ max unit t 1 standby entry complete (eof hard standby) 1 frame + 16742 C 1 frame + 17032 extclks t 2 active extclk required after standby asserted 10 C C extclks t 3 active extclk required before standby de- asserted 10 C C extclks t 4 standby pulse width 1 frame + 16762 C C extclks ext clk standby mode t 1 t 2 t 4 t 3 standby asserted standby mode extclk disabled extclk enabled
mt9v115 ds rev. e pub. 5/15 en 13 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description entering standby mode 1. set sysctl 0x0018[0] to ?1? to initiate standby mode. 2. check until sysctl 0x0018[14] changes to ?1? to indicate mt9v115 is in standby mode. 3. turn extclk off. exiting standby mode 1. turn extclk on. 2. reset sysctl register 0x0018[0] to ?0.? 3. check until sysctl register 0x0018[14] changes to ?0?. note: steps 1 is only necessary in soft st andby mode if extclk is turned off. figure 4: soft standby mode operation module id the mt9v115 provides 4 bits of module id th at can be read by the host processor from register 0x001a[15:12]. the module id is programmed through the otpm. table 7: soft standby signal timing symbol parameter min typ max unit t 1 standby entry complete (0x301a[4] = 1) 1 frame + 16742 C 1 frame + 17032 extclks t 2 active extclk required after soft standby activates 10 C C extclks t 3 active extclk required before soft standby de-activates 10 C C extclks t 4 minimum standby time 1 frame + 16762 C C extclks ext clk sysctl 0x0018[0] mode t 1 t 2 t 4 t 3 standby asserted standby mode extclk disabled extclk enabled
mt9v115 ds rev. e pub. 5/15 en 14 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description parallel image data output interface the user can use the 8-bit parallel output (d out[7:0])to transmit the sensor image data in 8-bit yuv or in 8+2 bayer formats to the host system as shown in figure 5 for pixel data timing within a line and in figure 6 for frame and line timing structures. the mt9v115 has an output fifo to retain a constant pixel output clock independent from the data output rate variations due to scaling factor (used only in 8-bit yuv). the mt9v115 image data is read out in a pr ogressive scan mode. valid image data is surrounded by horizontal blanking and vert ical blanking. the amount of horizontal blanking and vertical bl anking are programmable. mt9v115 output data is synchronized with the pixclk output. when line_valid(lv) is high, one pixel value (10-bit bayer data) is output through pixclk period as shown in figure 5. pixclk is continuously runnin g as default even during the blanking period.the mt9v115 can be programmed to delay the pixclk edge relative to the d out transitions. also, pixclk phase can be programmed by the user. figure 5: pixel data timing example: 8+2 bayer format figure 6: frame timing, fv, and lv structure note: 1. p: frame start and end blanking time. 2. a: active data time. 3. q: horizontal blanking time p 0 (9:2) p 0 (1:0) p 1 (9:2) p 1 (1:0) p 2 (9:2) p n-1 (9:2) p n (9:2) line_valid pixclk d out [7:0] blanking blanking bayer 8+2 pixel data p n-1 (1:0) p n (1:0) frame_valid line_valid data modes p 1 a 2 q 3 a q a p
mt9v115 ds rev. e pub. 5/15 en 15 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description serial port this section describes how frames of pixel data are represented on the high-speed mipi serial interface. the mipi output transmitte r implements a serial differential sub-lvds transmitter capable of up to 176 mb/s. it supp orts multiple formats, error checking, and custom short packets. when the sensor is in the hard standby system state or in the soft standby system state, the mipi signals (clk_p, clk_n, data_p, data_n) indicate ultra low power state (ulps) corresponding to (nominal) 0v levels being driven on clk_p, clk_n, data_p, and data_n. this is equivalent to signaling code lp-00. when the sensor enters the streaming state, the interface goes through the following transitions: 1. after the pll has locked and the bias genera tor for the mipi drivers has stabilized, the mipi interface transitions from the ulps st ate to the ulps-exit state (signaling code lp?10). 2. after a delay (twakeup), the mipi interface transitions from the ulps-exit state to the tx-stop state (signaling code lp?11). 3. after a short period of time (the programme d integration time plus a fixed overhead), frames of pixel data start to be transmitted on the mipi interface. each frame of pixel data is transmitted as a number of high-speed packets. the transition from the txstop state to the high-speed signaling st ates occurs in accordance with the mipi specifications. between high-speed packets and between frames, the mipi interface idles in the tx- stop state. the transition from the high-s peed signaling states and the tx-stop state takes place in accordance with the mipi specifications. 4. if the sensor is reset, any frame in prog ress is aborted immediately and the mipi sig- nals switch to indicate the ulps. 5. if the sensor is taken out of the stream ing system state and sysctl r0x0042[0] = 1 (standby end-of-frame), any frame in pr ogress is completed and the mipi signals switch to indicate the ulps. if the sensor is taken out of the stream ing system state and sysctl r0x0042[0] = 0 (standby end-of-line), any frame in progress is aborted as follows: 1. any long packet in transmission is completed. 2. the end of frame short packet is transmitted. after the frame has been aborted, the mipi signals switch to indicate the ulps.
mt9v115 ds rev. e pub. 5/15 en 16 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description sensor control the sensor core of the mt9v115 is a progress ive-scan sensor that generates a stream of pixel data at a constant frame rate. figure 7 shows a block diagram of the sensor core. it includes the vga active-pixel array. the ti ming and control circuitry sequences through the rows of the array, resetting and then read ing each row in turn. in the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been selected, the data from each column is sequenced through an analog signal chain, including offset corr ection, gain adjustment, and adc. the final stage of the sensor core converts the output of the adc into 10-bit data for each pixel in the array. the pixel array contains optically active and light-shielded (dark) pixels. the dark pixels are used to provide data for the offset-correction algorithms (black level control). the sensor core contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. these registers are controlled by th e mcu firmware and are also accessible by the host processor through the two-wire serial interface. the output from the sensor core is a bayer pattern; alternate rows are a sequence of either red and green pixels or blue and gree n pixels. the offset and gain stages of the analog signal chain provide per-color control of the pixel data. figure 7: sensor core block diagram sensor core control registers system control 10-bit data out g1/g2 r/b g1/g2 r/b green1/green2 channel red/blue channel vga active-pixel sensor (aps) array analog processing adc digital processing timing and control
mt9v115 ds rev. e pub. 5/15 en 17 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description the sensor core uses a bayer color pattern, as shown in figure 8. the even-numbered rows contain green and red pixels; odd-numbered rows contain blue and green pixels. even-numbered columns contain green and blue pixels; odd-numbered columns contain red and green pixels. figure 8: pixel color pattern detail the mt9v115 sensor core pixel array is shown which reflects the layout of the array on the die. figure 9 on page 18 shows the image shown in the sensor during normal opera- tion. when the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced. column readout direction row readout direction black pixels first clear pixel gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r
mt9v115 ds rev. e pub. 5/15 en 18 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description figure 9: imaging a scene the sensor core supports different readout opti ons to modify the image before it is sent to the ifp. the readout can be limited to a spec ific window size of the original pixel array. by changing the readout order, the image can be mirrored in the horizontal direction. the image output size is set by programmi ng row and column start and end address registers. the four edge pixels in the 648 x 488 array are present to avoid edge effects and are not included in the visible window. when the sensor is configured to mirror the image horizontally, the order of pixel readout within a row is reversed, so that read out starts from the last column address and ends at the first column address. figure 10 shows a sequence of 6 pixels being read out with normal readout and reverse readout. this change in sensor core output is corrected by the ifp. figure 10: six pixels in normal and column mirror readout mode lens pixel (0,0) row readout order column readout order scene sensor (rear view) d out [9:0] line_valid normal readout g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) r2 (9:0) reverse readout g2 (9:0) r2 (9:0) r1 (9:0) g1 (9:0) r0 (9:0) g0 (9:0) d out [9:0]
mt9v115 ds rev. e pub. 5/15 en 19 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description figure 11: eight pixels in normal and column skip 2x readout mode figure 12 on page 19 through figure on page 21 show the different skipping modes supported in mt9v115. figure 12: pixel readout (no skipping) d out [9:0] line_valid normal readout g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) g3 (9:0) r3 (9:0) d out [9:0] line_valid column skip readout g0 (9:0) r0 (9:0) g2 (9:0) r2 (9:0) r2 (9:0) x incrementing y incrementing
mt9v115 ds rev. e pub. 5/15 en 20 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description figure 13: pixel readout (x_odd_inc = 3, y_odd_inc = 1) x incrementing y incrementing
mt9v115 ds rev. e pub. 5/15 en 21 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description image flow processor image control processing in th e mt9v115 is implemented in the ifp hardware logic. the ifp registers can be programmed by the ho st processor. for normal operation, the microcontroller automatically adjusts the operational parameters of the ifp. figure 14 shows the image data processing flow within the ifp. figure 14: image flow processor vga pixel array adc raw data raw 10 digital gain control, shading correction defect correction, nosie reduction, color interpolation, mux ifp color correction aperture correction gamma correction (10-to-8 lookup) statistics engine color kill scaler output formatting yuv to rgb 10/12-bit rgb 8-bit rgb 8-bit yuv rgb to yuv tx fifo parallel /mipi output output interface output mux test pattern hue rotate
mt9v115 ds rev. e pub. 5/15 en 22 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description for normal operation of the mt9v115, streams of raw image data from the sensor core are continuously fed into the color pipeline. the mt9v115 features an automatic color bar test pattern genera tion function to emulate sensor images as shown in figure 15 on page 23. figure 15: color bar test pattern test pattern example field_wr= seq_cmd, 0x15 // solid color reg=0x3072, 0x0200 // red reg=0x3074, 0x0200 // green red reg=0x3076, 0x0200 // blue reg=0x3078, 0x0200 // green blue field_wr= seq_cmd, 0x16 //100% color bar field_wr= seq_cmd, 0x17 //fade to gray field_wr= seq_cmd, 0x18 // pseudo random field_wr= seq_cmd, 0x19 // marching ones
mt9v115 ds rev. e pub. 5/15 en 23 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description image corrections image stream processing starts with the multiplication of all pixel values by a program- mable digital gain. this can be independently set to separate values for each color channel (r, gr, gb, b). independent color channel digital gain can be adjusted with vari- ables. lenses tend to produce images whose bright ness is significantly attenuated near the edges. there are also other factors causing fixed pattern signal gradients in images captured by image sensors. the cumulative result of all these factors is known as image shading. the mt9v115 has an embedded shading correction module that can be programmed to counter the shading effects on each individual r, gb, gr, and b color signal. the ifp performs continuous de fect correction that can mask pixel array defects such as high dark-current (hot) pixels and pixels that are darker or brighter than their neighbors due to photoresponse nonuniformity. the modu le is edge-aware with exposure that is based on configurable thresholds. the thre sholds are changed continuously based on the brightness of the current scene. enabling and disabling noise reduction, and setting thresholds can be defined through variable settings. color interpolation and edge detection in the raw data stream fed by the sensor core to the ifp, each pixel is represented by a 10-bit integer, which can be considered proportional to the pixel?s response to a one- color light stimulus, red, green, or blue, depending on the pixel?s position under the color filter array. initial data processing step s, up to and including the defect correction, preserve the one-color-per-pixel nature of th e data stream, but after the defect correc- tion it must be converted to a three-colors -per-pixel stream appropriate for standard color processing. the conversion is done by an edge-sensitive color interpolation module. the module adds the incomplete color information available for each pixel with information extracted from an appropri ate set of neighboring pixels. the algorithm used to select this set and extract the in formation seeks the best compromise between preserving edges and filtering out high-frequency noise in flat field areas. the edge threshold can be set th rough variable settings. color correction and aperture correction to achieve good color fidelity of the ifp outp ut, interpolated rgb values of all pixels are subjected to color correction. the ifp multiplies each vector of three pixel colors by a 3 x 3 color correction matrix. the color correction matrix can either be programmed by the user or automatically selected by the awb algorithm implemented in the ifp. color correction should ideally produce output colors that are independent of the spectral sensitivity and color crosstalk characteristics of the image sensor. the optimal values of the color correction matrix elements depend on those sensor characteristics. the color correction variables can be adjusted through variable settings. to increase image sharpness, a programmable 2d aperture correction (sharpening filter) is applied to color-corrected image data. the gain and threshold for 2d correction can be defined through variable settings.
mt9v115 ds rev. e pub. 5/15 en 24 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description gamma correction the gamma correction curve (as shown in figure 16) is implemented as a piecewise linear function with 19 knee points, taking 12-bit arguments and mapping them to 8-bit output. the abscissas of the knee points are fixed at 0, 64, 128, 256, 512, 768, 1024, 1280, 1536, 1792, 2048, 2304, 2560, 2816, 3072, 3328, 3584, 3840, and 4096. the mt9v115 ifp includes a block for gamma correction that has the capability to adjust its shape, based on brightness, to enhance the performance under certain lighting conditions. two custom gamma correction tables may be uploaded, one corre- sponding to a high lighting condition, the other one corresponding to a low lighting condition. the final gamma correction tabl e used depends on th e brightness of the scene and can take the form of either uploaded tables or an interpolated version of the two tables. a single (non-adjusting) tabl e for all conditions can also be used. figure 16: gamma correction curve special effects like negative image, sepia solarization, or b/w can be applied to the data stream at this point. these effects can be enabled and selected by cam_select_fx vari- able. to remove high- or low-light color artifacts, a color kill circuit is included. it affects only pixels whose luminance exceeds a certain preprogrammed threshold. the u and v values of those pixels are attenuated proporti onally to the difference between their lumi- nance and the threshold. gamma correction 0 50 100 150 200 250 300 0 1000 2000 3000 4000 input rgb, 12-bit output rgb, 8-bit 0.45
mt9v115 ds rev. e pub. 5/15 en 25 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description image scaling and cropping to ensure that the size of images output by the mt9v115 can be tailored to the needs of all users, the ifp includes a scaler module. when enabled, this module performs resca- ling of incoming images?shrin ks them to selected width and height without reducing the field of view and without discarding any pixel values. the scaler ratios are automati- cally computed from image output size and the fov. the scaled output must not be greater than 352. output widths greater than this must not use the scaler but instead must reduce the field of view. by configuring the cropped and output wind ows to various sizes, different zooming levels such as 4x, 2x, and 1x can be achieved. the height and width definitions for the output window must be equal to or smalle r than the cropped image. the image crop- ping and scaler module can be used together to implement a digital zoom. hue rotate the mt9v115 has integrated hue rotate. this feature will help for improving the color image quality and give customers the flexibility for fine color adjustment and special color effects. figure 17: 0 hue cam var8= 0xa00f, 0x00 // cam_hue_angle
mt9v115 ds rev. e pub. 5/15 en 26 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description figure 18: C22 hue figure 19: +22 hue cam var8= 0xa00f, 0xea // cam_hue_angle cam var8= 0xa00f, 0x16 // cam_hue_angle
mt9v115 ds rev. e pub. 5/15 en 27 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description auto exposure the ae algorithm performs automatic adjustments of the image brightness by controlling exposure time, and analog gains of the sensor core as well as digital gains applied to the image. the ae algorithm analyzes image statistics collected by the exposure measurement engine, and then programs the sensor core and color pipeline to achieve the desired exposure. ae uses 4 x 4 exposure statistics windows, which can be scaled in size to cover any portion of the image. the mt9v115 uses average brightness tracking (average y), which uses a constant average tracking algorithm where a target brightness value is compared to a current brightness value, and the gain and integration time are adjusted accordingly to meet the target requirement. the mt9v115 also has a weighted ae algorithm that allows the sensor to be configured to respond to scene illuminance based on each of the weights in the 4 x 4 exposure statistics windows. the auto exposure can be configured to respond to scene illuminance based on certain criteria by adjusting gains and integr ation time based on scene brightness. auto white balance the mt9v115 has a built-in awb algorithm de signed to compensate for the effects of changing spectra of the scene illumination on the quality of the color rendition. the algorithm consists of two major parts: a measurement engine performing statistical analysis of the image and a module performing the selection of the optimal color correc- tion matrix, digital, and sensor core analog gains. while default settings of these algo- rithms are adequate in most situations, th e user can reprogram base color correction matrices and place limits on color channel gains. the awb algorithm estimates the dominant co lor temperature of a light source in a scene and adjusts the b/g, r/g gain ratios accordingly to produce an image for srgb display in which grey and white surfaces ar e reproduced faithfully. this usually means that r,g,b are roughly equal for thes e surfaces hence the word ?balance?. the awb algorithm uses statistics collected fr om the last frame to calculate the required b/g and r/g ratios and set the blue and red analog sensor gains and digital soc gains to reproduce the most accurate grey and white surfaces in future frames. flicker detection and avoidance flicker occurs when the integration time is not an integer multiple of the period of the light intensity. the automatic flicker dete ction module does not compensate for the flicker, but rather avoids it by detecting the flicker frequency and adjusting the integra- tion time. for integration times below the light intensity period (10ms for 50hz environ- ment, 8.33ms for 60hz environment), flicker cannot be avoided. while this fast flickering is marginally detectable by the human eye, it is very noticeable in digital images because the flicker period of the light source is very close to the range of digital images? exposure times. many cmos sensors use a ?rolling shutter? readout mechanism that greatly improves sensor data readout times. this allows pixel data to be read out much sooner than other methods that wait until the entire exposure is complete before reading out the first pixel data. the rolling shutter mechanism exposes a range of pixel rows at a time. this range of exposed pixels starts at the top of the image and then ?rolls? down to the bottom
mt9v115 ds rev. e pub. 5/15 en 28 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description during the exposure period of the frame. as each pixel row completes its exposure, it is ready to be read out. if the light source osci llates (flickers) during this rolling shutter exposure period, the image appears to have alternating light and dark horizontal bands. if the sensor uses the traditional snapshot readout mechanism, in which all pixels are exposed at the same time and then the pixel data is read out, then the image may appear overexposed or underexposed due to light fluctuations from the flickering light source. lights operating on ac electric systems prod uce light flickering at a frequency of 100hz or 120hz, twice the freq uency of the power line. to avoid this flicker effect, the exposure ti mes must be multiples of the light source flicker periods. for example, in a scene lit by 60hz ac power source, the available expo- sure times are 8.33ms (1/120), 16.67ms, 25ms, 33.33ms, and so on. in this case, the ae algorithm must limit the integration time to an integer multiple of the light?s flicker period. by default, the mt9v115 does all of this auto matically, ensuring that all exposure times avoid any noticeable light flicker in the scene. the mt9v115 ae algorithm is always setting exposure times to be integer multipliers of either 100hz (for 50hz ac power source) or 120hz (for 60hz ac power source). the flicker detection module keeps moni- toring the incoming frames to detect whet her the scene's lighting has changed to the other of the two light source frequencies. a 50hz/60hz tungsten lamp can be used to calibrate the flicker detect settings. output conversion and formatting the yuv data stream can either exit the color pi peline as is or be converted before exit to an alternative yuv or rgb data format. color conversion formulas y'u'v' this conversion is bt 601 scaled to make yuv range from 0 through 255. this setting is recommended for jpeg encoding and is the most popular, although it is not well defined and often misused in various operating systems. (eq 1) (eq 2) (eq 3) there is an option where 128 is not added to u'v'. y'cb'cr' using srgb formulas the mt9v115 implements the srgb standard. this option provides ycbcr coefficients for a correct 4:2:2 transmission. note: 16 < y601< 235; 16 < cb < 240; 16 < cr < 240; and 0 < = rgb < = 255 (eq 4) (eq 5) (eq 6) y ? 0.299 r ? 0.587 g ? 0.114 b ? ? + ? + ? = u ? 0.564 (b ? y ? ? ? 128 + ? = v ? 0.713 (r ? y ? ? ? 128 + ? = y ? (0.2126 r ? 0.7152 g ? 0.0722 b ? ? (219 256) + 16 ? ? ? + ? + ? = cb ? 0.5389 (b ? y ? ? (224 256) + 128 ? ? ? ? = cr ? 0.635 (r ? y ? ? (224 256) + 128 ? ? ? ? =
mt9v115 ds rev. e pub. 5/15 en 29 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description y'u'v' using srgb formulas these are similar to the previous set of formulas, but have yuv spanning a range of 0 through 255. (eq 7) (eq 8) (eq 9) there is an option to disable adding 128 to u'v'. the reverse transform is as follows: (eq 10) (eq 11) (eq 12) uncompressed yuv/rgb data ordering the mt9v115 supports swapping ycbcr mode, as illustrated in table 8. the rgb output data ordering in default mode is shown in table 9. the odd and even bytes are swapped when luma/chroma swap is enabled. r and b channels are bitwise swapped when chroma swap is enabled. uncompressed 10-bit bypass output raw 10-bit bayer data from the sensor core can be output in bypass mode by using d out [7:0] with a special 8 + 2 data format, shown in table 10. table 8: ycbcr output data ordering mode data sequence default (no swap) cb i y i cr i y i+1 swapped crcb cr i y i cb i y i+1 swapped yc y i cb i y i+1 cr i swapped crcb, yc y i cr i y i+1 cb i table 9: rgb ordering in default mode mode (swap disabled) byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 565rgb odd r 7 r 6 r 5 r 4 r 3 g 7 g 6 g 5 even g 4 g 3 g 2 b 7 b 6 b 5 b 4 b 3 table 10: 2-byte bayer format byte bits used bit sequence odd bytes 8 data bits d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 even bytes 2 data bits + 6 unused bits 0 0 0 0 0 0 d 1 d 0 y ? 0.2126 r ? 0.7152 g ? 0.0722 b ? ? + ? + ? = u ? 0.5389 (b ? y ? ) ? 128 0.1146 ? r ' 0.3854 g ' 0.5 b ' 128 + ? + ? ? ? = + ? = v ? 0.635 (r ? y ? ? ? ? 128 0.5 r ' 0.4542 g ' 0.0458 b ' 128 + ? ? ? ? ? = + = r ? y 1.5748 v ? 128 ? + = g ? y 0.1873 (u 128 ? ? ? ? 0.4681 (v 128) ? ? ? = b ? y 1.8556 (u 128) ? ? + =
mt9v115 ds rev. e pub. 5/15 en 30 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor functional description note: data will be packed as raw8 if the data type specified does not match any of the above data types. bt656 yuv data can also be output in bt656 format with odd sav/eav codes. the bt656 data output will be progress ive data and not interlaced (r0x3c00[5] = 1). figure 20: bt656 image data with odd sav/eav codes defect correction(dc) and noise reduction(nr) there is also a third output conversion format dcnr which is available in both mipi and parallel mode. dcnr mode allows the image to be either defect corrected or noise corrected. in mipi mode it is available as 10 bit output and in parallel as 8+2 bit output. there is a restriction on the number of lines as four are removed for the process resulting in a maximum 648 x484 output. table 11: data formats supported by mipi interface data format data type yuv 422 8-bit 0x1e 565rgb 0x22 raw8 0x2a raw10 0x2b active video data [7:0] line valid fram e valid cbycry cbycry 80 10 80 10 80 10 10 80 10 80 10 80 10 80 10 cb y cr y ff 00 00 80 80 ff 00 00 9d ff 00 00 80 cb y cr y 80 10 80 10 ff 00 00 b6 sav im age eav sav im age eav hblank hblank blanking blanking blanking hblank
mt9v115 ds rev. e pub. 5/15 en 31 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor register and variable description register and variable description to change internal registers and ram vari ables of mt9v115, use the two-wire serial interface through the external host device. note: for more detailed information on mt9v115 registers and variables, see the mt9v115 register and variable reference. the sequencer is responsible for coordinating all events triggered by the user. the sequencer provides the high-level cont rol of the mt9v115. commands are written to the command variable to start streaming, stop streaming, and to select test pattern modes. command execution is confirmed by reading back the command variable with a value of zero. the sequencer state variable can also be checked for transition to the desired state. all configuration of the sensor (start/stop row/column, mirror, skipping) and the soc (image size, format) and automati c algorithms for ae, awb, low light, are performed when the sequencer is in the stopped state. when the sequencer is in the idle or test pattern state the algorithms and register updates are not performed, allowing the host complete manual control. table 12: summary of mt9v115 variables name variable description monitor variables general information sequencer variables programming control interface advanced control variables advanced control variables information fd variables flicker detect ae_track variables auto exposure awb variables auto white balance stat variables statistics low light variables low light cam variables camera controls
mt9v115 ds rev. e pub. 5/15 en 32 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor register and variable description two-wire serial interface the two-wire serial interface bus enables re ad and write access to control and status registers within the mt9v115. the interface protocol uses a master/slave model in which a master controls one or more slave devices. the mt9v115 always op erates in slave mode. the host (master) generates a clock (sclk) that is an input to the mt9v115 and is used to synchronize transfers. data is transferred between the master and the slave on a bidirectional signal (s data ). protocol data transfers on the two-wire serial interf ace bus are performed by a sequence of low- level protocol elements, as follows: 1. a (repeated) start condition 2. a slave address/data direction byte 3. a 16-bit register address (8-bit addresses are not supported) 4. an (a no) acknowledge bit 5. a 16-bit data transfer (8-bit data tran sfers are supported using xdma byte access) 6. a stop condition the bus is idle when both sclk and s data are high. control of the bus is initiated with a start condition, and the bus is released with a stop condition. only the master can generate the start and stop conditions. a start condition is defined as a high-to-low transition on s data while sclk is high. at the end of a transfer, the master can generate a start condition without previously generating a stop cond ition; this is known as a repe ated start or restart condition. a stop condition is defined as a low-to-high transition on s data while sclk is high. data is transferred serially, 8 bits at a ti me, with the most significant bit (msb) trans- mitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for th e slave address/data direction byte and for message bytes. one data bit is transferred during each sclk clock period. s data can change when sclk is low and must be stable while sclk is high. mt9v115 slave address bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. the slave address default is 0x7a. messages message bytes are used for sending mt9v115 internal register addresses and data. the host should always use 16-bit address (two by tes) and 16-bit data to access internal registers. refer to read and write cycles in figure 21 on page 34 through figure 25 on page 36. each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the sclk clock period following the data transfer . the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowl- edge bit by driving s data low. for data transfers, s data can change when sclk is low and must be stable while sclk is high.
mt9v115 ds rev. e pub. 5/15 en 33 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor register and variable description the no-acknowledge bit is generated when the receiver does not drive s data low during the sclk clock period following a data transf er. a no-acknowledge bit is used to termi- nate a read sequence. typical operation a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the requ est is for a read or a write, where a ?0? indicates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. if the request was a write, the master then tr ansfers the 16-bit register address to which a write will take place. this transfer take s place as two 8-bit sequences and the slave sends an acknowledge bit after each sequen ce to indicate that the byte has been received. the master will then transfer the 16-bit data, as two 8-bit sequences and the slave sends an acknowledge bit after each sequ ence to indicate that the byte has been received. the master stops writing by generat ing a (re)start or stop condition. if the request was a read, the master sends the 8-bi t write slave address/data direction byte and 16-bit register address, just as in the write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. the mast er generates an acknowledge bit after each 8-bit transfer. the data transfer is stopped when the master sends a no-acknowledge bit. single read from random location figure 21 shows the typical read cycle of the host to mt9v115. the first 2 bytes sent by the host are an internal 16-bit register address. the following 2-byte read cycle sends the contents of the registers to host. figure 21: single read from random location s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave slave address 0 s a reg address[15:8] a reg address[7:0] slave address a a 1 sr read data p previous reg address, n reg address, m m+1 a
mt9v115 ds rev. e pub. 5/15 en 34 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor register and variable description single read from current location figure 22 shows the single read cycle without writing the address. the internal address will use the previous address value written to the register. figure 22: single read from current location sequential read, start from random location this sequence (figure 23) starts in the same way as the single read from random loca- tion (figure 21 on page 34). instead of gener ating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 23: sequential read, start from random location sequential read, start from current location this sequence (figure 24) starts in the same way as the single read from current loca- tion (figure 22). instead of generating a no-a cknowledge bit after the first byte of data has been transferred, the master genera tes an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 24: sequential read, start from current location slave address 1 s a read data [15:8] slave address a 1 s p read data [15:8] p previous reg address, n reg address, n+1 n+2 a a read data [7:0] a read data [7:0] a a read data read data previous reg address, n n+1 n+2 n+l-1 a read data slave address a a 1 read data a s slave address 0 s sr a reg address[15:8] a read data read data a reg address[7:0] a read data slave address previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a 1 a a read data read data m+l-2 m+l-1 m+l a s a read data read data previous reg address, n n+1 n+2 n+l-1 n+l a read data slave address a a 1 read data a s s
mt9v115 ds rev. e pub. 5/15 en 35 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor register and variable description single write to random location figure 25 shows the typical write cycle from the host to the mt9v115. the first 2 bytes indicate a 16-bit address of the internal registers with most-significant byte first. the following 2 bytes indicate the 16-bit data. figure 25: single write to random location sequential write, start at random location this sequence (figure 26) starts in the same way as the single write to random location (figure 25). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until ?l? bytes have been writte n. the write is terminated by the master generating a st op condition. figure 26: sequential write, start at random location slave address 0 s a reg address[15:8] a reg address[7:0] a write data p previous reg address, n reg address, m m+1 a a slave address 0 s a reg address[15:8] a write data write data a reg address[7:0] a write data previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a write data write data m+l-2 m+l-1 m+l a a s
mt9v115 ds rev. e pub. 5/15 en 36 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor slave address selection in dual camera application (only for parallel not sup- slave address selection in dual camera application (only for parallel not supported in serial) the mt9v115 offers a special function specific ally for mobile phone applications. this is the ability to connect two image sensors in a dual-camera configuration. a block diagram of this mode is shown in figure 27. by toggling between the two standby pins, the image data can be taken off either image sensor. figure 27: dual camera the process for changing the slave address for camera b is set out below: 1. power up camera a (0x7a) and b (0x7a). with hard standby asserted. (both camera a and b are in hard standby) 2. take camera b out of hard standby 3. change the address of camera b (0x78) by writing to a register. 4. put camera b back to hard standby 5. take camera a out of hard standby. camera a (0x7a) and camera b (0x78) now have different slave addresses. one-time programming memory (otpm) the mt9v115 has one-time programmable memory (otpm) for supporting defect correction, module id, and other customer-related information. there are 2784 bits of otpm available for these listed features. the otpm can be programmed when the v pp voltage is applied. mt9v115 s clk s data standby extclk v dd _io v dd v dd _pll v aa 1.8v 2.8v gnd_io d gnd gn d_pll a gnd fv lv pixclk d out [7 : 0 ] d gnd a gnd v pp s clk s data standby extclk v dd _io v dd v dd _p ll v aa 1.8v 2.8v gnd_io d gnd gnd_pll a gnd fv lv pixclk d out [7: 0] d gnd a gnd v pp mclk standby_1 vpp mclk standby_2 vpp rpullup rpullup camera a camera b sclk s data sclk s data v dd _phy v dd _phy data_n data_p data_n mt9v115 data_p
mt9v115 ds rev. e pub. 5/15 en 38 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor spectral characteristics spectral characteristics figure 28: chief ray angle (cra) vs. image height cra vs. image height plot image height cra (%) (mm) (deg) 000 5 0.035 1.23 10 0.070 2.46 15 0.105 3.70 20 0.140 4.94 25 0.175 6.18 30 0.210 7.43 35 0.245 8.67 40 0.280 9.90 45 0.315 11.13 50 0.350 12.36 55 0.385 13.57 60 0.420 14.77 65 0.455 15.97 70 0.490 17.14 75 0.525 18.31 80 0.560 19.45 85 0.595 20.58 90 0.630 21.69 95 0.665 22.77 100 0.700 23.83 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 102030405060708090100110 cra (deg) image height (%)
mt9v115 ds rev. e pub. 5/15 en 39 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor spectral characteristics figure 29: quantum efficiency 0 10 20 30 40 50 60 390 410 430 450 470 490 510 530 550 570 590 610 630 650 670 690 710 730 750 770 790 810 830 850 870 890 910 930 950 970 990 1010 1030 1050 1070 1090 r gr gb b wavelength (nm) qe (%)
mt9v115 ds rev. e pub. 5/15 en 40 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor electrical specifications electrical specifications caution stresses above those listed in table 13 may cause permanent damage to the device. note: this is a stress rating only, and functional oper ation of the device at these or any other conditions above those indicated in the product specification is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. recommended operating conditions table 13: absolute maximum ratings symbol parameter rating unit min max v dd core digital voltage C0.3 2.4 v v dd _io i/o digital voltage C0.3 4.0 v v aa analog voltage C0.3 4.0 v v aa _pix pixel supply voltage C0.3 4.0 v v dd _pll pll supply voltage C0.3 4.0 v v pp otpm power supply 7.5 9.5 v v in input voltage C0.3 v dd _io + 0.3 v t op operating temperature (measure at junction) C30 70 c t stg 1 storage temperature C40 85 c table 14: operating conditions symbol parameter min typ max units v dd core digital voltage 1.7 1.8 1.95 v v dd _io i/o digital voltage 2.5 2.8 3.1 v 1.7 1.8 1.95 v v aa analog voltage 2.5 2.8 3.1 v v dd _phy mipi supply voltage 2.5 in mipi mode v dd _io in parallel mode 2.8 in mipi mode v dd _io in parallel mode 3.1 in mipi mode v dd _io in parallel mode v v aa _pix pixel supply voltage 2.5 2.8 3.1 v v dd _pll pll supply voltage 2.5 2.8 3.1 v v pp otpm power supply 8.5 8.5 9 v t j operating temperature (at junction) C30 55 70 c
mt9v115 ds rev. e pub. 5/15 en 41 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor electrical specifications note: 1. this does not include v dd _io current. table 15: dc electrical characteristics symbol parameter condition min max unit v ih input high voltage 0.7 * v dd _io v dd _io + 0.5 v v il input low voltage C0.3 0.3 * v dd _io v i in input leakage current v in = 0v or v in = v dd _io 10 ? a v oh output high voltage v dd _io = 1.8v, i oh = 2ma 1.7 C v v dd _io = 1.8v, i oh = 4ma 1.6 C v v dd _io = 1.8v, i oh = 8ma 1.4 C v v dd _io = 2.8v, i oh = 2ma 2.7 C v v dd _io = 2.8v, i oh = 4ma 2.6 C v v dd _io = 2.8v, i oh = 8ma 2.5 C v v ol output low voltage v dd _io = 1.8v, i oh = 2ma C 0.1 v v dd _io = 1.8v, i oh = 4ma C 0.2 v v dd _io = 1.8v, i oh = 8ma C 0.4 v v dd _io = 2.8v, i oh = 2ma C 0.1 v v dd _io = 2.8v, i oh = 4ma C 0.2 v v dd _io = 2.8v, i oh = 8ma C 0.4 v table 16: operating/standby current consumption f extclk = 44 mhz; f pixclk = 22 mhz; voltages = typ; t j = typ; excludes v dd _io current symbol parameter condition typ max unit i dd digital operating current 9 9.5 ma i aa analog operating current 8 8.5 ma i dd _pll pll supply current 5.5 6 ma total supply current 22.5 24 ma total power consumption 54 57.7 mw i dd (mipi) digital operating current 11 12 ma i aa (mipi) analog operating current 8 8.5 ma i dd _pll (mipi) pll supply current 5.5 6 ma i dd _phy (mipi) mipi phy supply current 6.5 7 ma total supply current (mipi) 31 33.5 ma total power consumption (mipi) 75.8 81.8 mw hard standby (clock off) total standby current when asserting the standby signal 19 22 a 1 standby power 45 53 w 1 soft standby (clock on) total standby current f extclk = 44 mhz, soft standby mode 2.3 2.5 ma 1 standby power 4.5 4.9 mw 1 soft standby (clock off) total standby current soft standby mode 19 22 a 1 standby power 45 53 w 1
mt9v115 ds rev. e pub. 5/15 en 42 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor electrical specifications notes: 1. pixclk output signal can be in verted internally by programming register. 2. it is only necessary to meet this spec when the pll is bypassed. if the pll is being using then vih/ vil should be met. table 17: ac electrical characteristics f extclk = 4C44 mhz; v dd = 1.8v; v dd _io = 1.8vC2.8v; v aa = 2.8v; vaa_pix = 2.8v; v dd _pll = 2.8v; c load = 30pf symbol parameter conditions min typ max unit note f extclk external clock frequency pll enabled 4 44 mhz t r input clock rise time C C 5 ns 2 t f input clock fall time C 5 ns 2 clock duty cycle 45C55% t jitter input clock jitter (peak-to-peak jitter) C 1 ns output signal slew rise and fall time of parallel output signals (pixclk fv, lv, d out ) with slew rate programmed to 7. see sysctl register 0x001e. v dd _io = 2.8v input clock = 48 mhz c load =30pf C 3 C ns c load = 50pf C 4 C ns rise and fall time of parallel output signals (pixclk, fv, lv, d out ) with slew rate programmed to 4. see sysctl register 0x001e. = c load =30pf C 4 C ns c load = 50pf C 5 C ns rise and fall time of parallel output signals (pixclk, fv, lv, d out ) with slew rate programmed to 0. see sysctl register 0x001e. v dd _io = 2.8v input clock = 48 mhz c load =30pf C 9 C ns c load = 50pf C 11 C ns f pixclk pixclk frequency C C 22 mhz 1 t pixclk_jitter pixel clock jitter (output jitter, peak- to-peak) 1.3 2.1 3.7 ns t pd pixclk to data valid input clock = 44 mhz, c load =30pf CC5ns t pfh pixclk to fv high C C 4 ns t plh pixclk to lv high C C 4 ns t pfl pixclk to fv low C C 4 ns t pll pixclk to lv low C C 4 ns c in input pin capacitance 7 C pf
mt9v115 ds rev. e pub. 5/15 en 43 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor electrical specifications figure 30: parallel pixel bus timing diagram notes: 1. pll disabled. 2. frame_valid leads line_valid by 6 pixclks. 3. frame_valid trails line_valid by 6 pixclks. 4. d out [7:0], frame_valid, and line_valid are shown with respect to the rising edge of pixclk. this feature is programmable and d out [7:0], frame_valid, and line_valid can be synchronized to the falling edge of pixclk. 5. propagation delay is measured fr om 50% of rising and falling edges table 18: mipi timing measurements: clock parameter mipi spec 1.0 min typical (median) max units register set to tclk-post >(60ns+52ui) 355.45 603 603 605 ns 0x3c52[8-13] 9 (13) teot <(102+12ui) 10.18 89 90 90 ns n/a n/a tclk-trail >60 78 78 78 ns 0x3c54[8-11] 2 ths-exit >100 5187 5189 5189 ns 0x3c50[8-13] 3 tlpx >50 90 91 92 ns 0x3c56[0-5] 2 tclk-prepare 38 C 95 61 63 65 ns 0x3c5a[2-3] 2 tclk-zero no spec 442 445 446 ns 0x3c54[0-5] 7 tclk-prepare & tclk-zero >300 508 508 509 ns n/a n/a tclk-pre >(8ui) 45.45 81 83 83 ns 0x3c52[0-5] 2 pixclk frame_valid, line_valid t pfl t pll t pfh t plh t pd 3 1 2 d out [7:0]
mt9v115 ds rev. e pub. 5/15 en 44 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor electrical specifications figure 31: mipi clock timing table 19: mipi timing measurements: data parameter mipi spec 1.0 min typical (median) max units register set to tlpx >50 92 93 93 ns 0x3c56[0-5] 2 ths-prepare (40+4ui)to (85+6ui) 62.73 C119.09 64 67 69 ns 0x3c5a[0-1] 2 ths-zero no spec 630 630 635 ns 0x3c4e[8-11] 5 ths-prepare & ths- zero >(145+10ui) >201.82 697 700 703 ns n/a n/a ths-trail >(60+4ui) & >(8ui) 82.73 -45.45 165 165 167 ns 0x3c50[0-3] 3 t clk-pre t clk-zero t clk-settle t clk-term-en t clk-prepare t lpx t hs-exit t clk-trail t eot t clk-miss t clk-post t lpx t hs-prepare t hs-settle t hs-zero t hs-skip v ih-min v il-max v ih-min v il-max
mt9v115 ds rev. e pub. 5/15 en 45 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor electrical specifications table 20: mipi high speed (hs) parameter mipi spec 1.0 min typical (median) max units |vod| hs transmit differential voltage 140 - 270 203 209 219 mv vcmtx hs transmit static common mode voltage 150 - 250 196 201 213 mv |vod| hs vod mismatch ? 10 2 5 7 mv |vcmtx(1,0)| vcmtx mismatch ?5 0 1 1 mv v ohhs hs output high voltage <360 300 308 322 mv zos single ended output impedance 40 C 62.5 43 45 46 zos single ended output impedance mismatch ? 10% 0.66 1.75 3.6 % tr 20%-80% rise time 150ps to 0.3ui (1.7ns) 322 364 408 ps tf 20%-80% fall time 150ps to 0.3ui (1.7ns) 351 397 438 ps eye width 5.581 ns ui error 0.2 0.0177 ui data to clock skew 0.15 0.006 0.004 0.001 ui |vod| hs transmit differential voltage 140 - 270 203 209 219 mv
mt9v115 ds rev. e pub. 5/15 en 46 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor electrical specifications figure 32: mipi data timing table 22: two-wire serial interface timing data f extclk = 14 mhz; v dd = 1.8v; v dd _io = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; t j = 70c; c load = 68.5pf table 21: mipi low power (lp) parameter mipi spec 1.0 min typical (median) max units vol output low level 50 4.12 6.70 13.9 mv voh output high level 1.1 C1.3 1.18 1.21 1.24 v zolp output impedance of lp ? 110 140 147 156 trlp 15%-85% rise time ? 25 142.8 15.27 15.86 ns tflp 15%-85% fall time ? 25 13.79 14.35 16.15 ns trlp 15%-85% rise time (heavy load) ? 25 12.18 13.19 13.62 ns tflp 15%-85% fall time (heavy load) ? 25 11.95 12.61 13.45 ns slew rate, (cload = 0pf) ? 500 n/a n/a n/a mv/ns slew rate, (cload = 5pf) ? 300 n/a n/a n/a mv/ns slew rate, (cload = 20pf) ? 250 62.1 91.81 151 mv/ns slew rate, (cload = 70pf) ? 150 69.39 76.06 85.32 mv/ns slew rate, (cload = 20pf) (heavy load) ? 250 94.9 117.2 179 mv/ns slew rate, (cload = 70pf) (heavy load) ? 150 55 91.85 102.65 mv/ns symbol parameter conditions min typ max unit f sclk serial interface input clock frequency 100 400 khz t sclk serial interface input clock period 2.5 10 ? s s clk duty cycle 50 55 % t low s clk low period 1 ? s v ih-min v il-max t hs-sync t hs- zero t hs-settle t d- term-en t hs- prepare t lpx t hs-trai l t eot t hsexi t t hs- ski p capture 1 st data bit t reot lp-11 lp-01 lp-00 lp-11 v idth(max) v term- en( max) disconnect terminator
mt9v115 ds rev. e pub. 5/15 en 47 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor electrical specifications t high s clk high period 1 ? s t rs clk /s data rise time 300 ns t srts start setup time master write to slave 600 ns t srth start hold time master write to slave 300 ns t sdh s data hold master write to slave 300 ns t sds s data setup master write to slave 300 ns t shaw s data hold to ack master read from slave 300 ns t ahsw ack hold to s data master read from slave 300 ns t stps stop setup time master write to slave 300 ns t stph stop hold time master write to slave 600 ns t shar s data hold to ack master write to slave 150 ns t ahsr ack hold to s data master write to slave 150 ns t sdhr s data hold master read from slave 300 650 ns t sdsr s data setup master read from slave 300 ns symbol parameter conditions min typ max unit
mt9v115 ds rev. e pub. 5/15 en 48 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor electrical specifications figure 33: two-wire serial bus timing parameters sclk s data sclk s data write start ack read start ack t shar t ahsr t sdhr t sdsr read sequence write sequence read address bit 7 read address bit 0 register value bit 7 register value bit 0 write address bit 7 write address bit 0 register value bit 7 register value bit 0 t srts t sclk t sdh t sds t shaw t ahsw stop t stps t stph t srth ack
mt9v115 ds rev. e pub. 5/15 en 49 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor power sequence power sequence power-up sequence powering up the sensor requires the supply rails to be applied in a particular order to ensure sensor start up in a normal operation and prevent undesired condition such as latch up from happening. refer to figure 34 andtable 23 for detailed timing require- ment. figure 34: power-up sequence table 23: power- up signal timing symbol parameter min typ max unit t1 delay from v dd to v aa and v dd _io and v dd _phy 0 C 500 ms t2 delay from v dd to v dd _pll 0 C 500 ms t3 extclk activation 0 500 C ms t4 internal por duration 70 - - extclks t5 first serial write 50 - - extclks t 2 v aa , vdd_io, vdd_phy v dd _pll v dd extclk t 3 t 1 t 4 internal por sclk sdata t 5
mt9v115 ds rev. e pub. 5/15 en 50 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor power sequence power-down sequence figure 35: power-down sequence note: 1. t3 is required between power down and next power up time, all decoupling caps from regulators must completely discharged before next power up. table 24: power-down supply rail timing definition symbol minimum typical maximum unit v dd to v dd _io and v dd _phy t1 0 - 500 ms v dd _io and v dd _phy to v aa t2 0 - 500 ms pwrdn until next pwrup time 1 t3 100 - - ms v dd _ io (2.8/1.8) v aa (2.8) v dd (1.8) power down until next power up c y t3 t2 t1
mt9v115 ds rev. e pub. 5/15 en 51 ?semiconductor components industries, llc, 2015. mt9v115: 1/13-inch vga soc digital image sensor revision history revision history rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/5/15 ? updated to on semiconductor template ? removed confidential marking ? updated ?ordering information? on page 2 rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9/29/11 ? updated table 16, ?operating/standby current consumption,? on page 41 rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/16/11 ?updated table1 on page1 ? updated figure 1 on page 6 ? updated figure 2 on page 8 ?updated table3 on page10 ?updated table4 on page10 ?updated ?power-on reset? on page11 ? updated ?exiting standby mode? on page 12 ? updated ?de-assert standby signal (low).? on page 12 ? updated ?entering standby mode? on page 13 ? updated figure 4 on page 13 ? updated?parallel image data output interface? on page 14 ? updated figure 5 on page 14 ? updated ?serial port? on page 15 ? replaced figure 14 on page 21 with new figure ? updated figure 15 on page 23 ? updated ?gamma correction? on page 25 ? updated figure 17, figure 18, and figure 19 ? updated ?flicker detection and avoidance? on page 28 ? updated table 12 on page 32 ? added figure 29: ?quantum efficiency,? on page 39 ? updated table 16, ?operating/standby current consumption,? on page 41 ? add table 18, table 19, table 20 and table 21 ? add figure 31 on page 44 and figure 32 on page 46 ? updated table 23 on page 49 and table 24 on page 50 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/13/10 ? added ?hard standby mode? on page 11 and?soft standby mode? on page 12 ? added ?power sequence? on page 48 ? updated table 1, ?key parameters,? on page 1 ? added note to?features? on page 1 ?updated ?power-on reset? on page11 ? added odd before ?bt656? on page 31 ? updated table 17, ?ac electrical characteristics,? on page 42
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. mt9v115: 1/13-inch vga soc digital image sensor revision history mt9v115 ds rev. e pub. 5/15 en 52 ?semiconductor components industries, llc, 2015 . a-pix is a trademark of semiconductor components industries, llc (s cillc) or its subsidiaries in the united states and/or other countries. rev. a, advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9/16/10 ?initial release.

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